1. Field of the Invention
The present invention is generally in the field of electronics. More particularly, the present invention is in the field of electronic circuit and logic design.
2. Background
The data propagation delay in conventional multiplexers can significantly delay the transmission of data in electronic circuits, thereby undesirably causing the circuits to operate slowly or even causing the circuits to malfunction. Furthermore, the data propagation delay can be substantially higher in larger multiplexers, such as 32-to-1 multiplexers, than in smaller multiplexers, such as two-to-one multiplexers. Thus, conventional multiplexers are unsuitable for many high speed circuit applications, such as a Scoreboard unit in a complex CPU, which typically require the use of large high speed multiplexers.
For example, one conventional multiplexer includes a configuration of complementary metal-oxide-semiconductor (“CMOS”) transmission gates arranged in a “tree structure.” However, such an implementation is impractical in large multiplexers (i.e., multiplexers having a large number of inputs), since it can disadvantageously result in the formation of long chains of series coupled CMOS transmission gates. In a 32-to-1 multiplexer, for example, as many as five CMOS transmission gates coupled in series can be required. These long chains of CMOS transmission gates can undesirably cause large propagation delays in the multiplexer and can substantially increase the noise sensitivity of the multiplexer.
Another conventional multiplexer includes at least one “wide” input logic gate, such as an eight-input OR gate. However, such an implementation is also impractical since wide input logic gates typically operate very slowly, and can therefore cause large propagation delays in the multiplexer.
Yet another conventional multiplexer includes low threshold voltage (“low VT”) devices, such as low VT logic gates, which can operate faster than conventional logic gates. However, the use of low VT devices is impractical in many applications due to their high cost. As such, the conventional multiplexers described above fail to provide a low cost, high speed multiplexer that is suitable for high speed circuit applications.